Cited Papers

Code Generation and Optimization

  • CGO#001: Jack W. Davidson, Christopher W. Fraser, "Automatic Generation of Peephole Optimizations", ACM/SIGPLAN PLDI, 2003.
    1. Ali-reza, et al., "Fast, Effective Code Generation in a Just-In-Time Java Compiler," In Proceedings of the ACM SIGPLAN'98 PLDI, pp280∼290, 1998.
    2. Gilled Muller et al., "Harissa: A Hybrid Approach to Java Execution," IEEE Software, Vol. 16 No. 2, 1999.
    3. Cheng-Hsueh A. Hsieh, John C. Gyllenhaal, and Wen-mei W. Hwu, "Java Bytecode to Native Code Translation: The Caffeine Prototype and Preliminary Results," Proceedings of the 29th International Symposium on Micro-architecture, pp90∼99, Dec. 1996.
    4. W. Paugh, "Compressing Java Class Files," In Proceedings of the ACM SIGPLAN'99 PLDI, pp.247∼258, 1999.
    5. Gilles Muller et al., "Java Bytecode Compression for Low-End Embedded Systems," ACM TOPLAS, Vol 22 No.3, pp471∼489, May 2000.
    6. SUIF Compiler System: http://suif.stanford.edu/

    Architecture Description Language

  • ADL#001: Christopher W. Fraser, David R. Hanson, "A Retargetable C Compiler: Design and Implementation," Addison-Wesley, 1995.
  • ADL#001: Christopher W. Fraser, David R. Hanson, "A Retargetable C Compiler: Design and Implementation," Addison-Wesley, 1995.
  • C. W. Fraser, "A Language for Writing for Code Generators," Proceedings of the SIGPLAN'89 PLDI, SIGPLAN Notices, 24(7), pp238-245, July 1989.
  • C. W. Fraser and D. R. Hanson, " A A Retargetable Compiler for ANSI C SIGPLAN Notices, 26(10), pp29-43, October 1991.
  • LCC, A Retargetable Compiler for ANSI C: http://www.cs.princeton.edu/software/lcc/
  • Andrew Appel, Jack Davidson, Norman Ramsey, "The Zephyr Compiler Infrastructure," Supercomputing 98, Nov. 1998.
  • The LANCE v2.0 System: http://LS12-www.cs.uni-dortmund.de/lance
  • Rainer Leupers, Retargetable Code Generation for Digital Signal Processors, Kluwer Academic Publishers, 1997.
  • P. Chang, S. Mahlke, W. Chen, N. Warter, W. Hwu, "IMPACT: An Architectural Framework for Multiple Instruction Issue Processors," 18th International Symposium on Computer Architecture, 1991.
  • A. Halambi, P. Grun, V. Ganesh, A. Khare, N.D. Dutt and A. Nicolau, "EXPRESSION: A Language for Architectural Exploration through Compiler/Simulator Retargetability," Proceedings of the 1999 Design, Automation and Test in Europe Conference, March 1999.
  • S. Pees, A. Hoffman, V. Zivojnovic, H. Meyr, "LISA-Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures," 36th Design Automation Conference, 1999.
  • A. Hoffman, A. Nohl, G, Braun, H. Meyr, "A Survey on Modeling Issues Using the Machine Description Language LISA," International Conference on Acoustics, Speech, and Signal Processing(ICASSP), 2001.
  • G. Goosens et al., "CHESS: Retargetable Code Generation for Embedded DSP Processors," Chap. 5 Kluwer Academic Publishers, 1997.
  • G. Goosens et al., "CHESS: Retargetable Code Generation for Embedded DSP Processors," In Code Generation for Embedded Processors, Kluwer Academic Publishers, 1997.
  • C. W. Fraser, D. R. Hanson, T. A. Proebsting, "Engineering a Simple, Efficient Code Generator Generator," ACM Letters on Programming Languages and Systems, Vol. 1 No. 3, 1992.
  • Rainer. Leupers, "Register Allocation for Common Subexpressions in DSP Data Paths," ASPDAC, 2000.
  • H. Emmelmann, F. Schroer, R. Landwehr, "BEG-A Generator for Efficient Backends," ACM SIGPLAN PLDI, SIGPLAN Notices 24, No. 7, 1989.
  • M. Freericks, "The nML Machine Description Formalism," Technical Report TR SM-IMP/DIST/08, TU Berlin Dept. CS, July 1993.
  • M. Ganapathi, C. N. Fischer, J. L. Hennessy, "Retargetable Compiler Code Generation," ACM Computing Survey, Vol. 14, No. 4, Dec. 1982.
  • A. V. Aho, M. Ganapathi, S. K. Tjiang, "Code Generation using Tree Matching and Dynamic Programming," ACM Trans. on Programming Language and Systems, Vol. 11, No. 4, Oct. 1989.
  • Rainer Leupers and Peter Marwedel, Retargetable Compiler Technology for Embedded Systems: Tools and Applications," Kluwer Academic Publishers, 2001.
  • Rainer Leupers, Wahlen O., et. al, "An Executable Intermediate Representation for Retargetable Compilation and High-Level Code Optimization," Int. Workshop on Systems, Architecture, Modeling and Simulation(SAMOS), July 2003.
  • Stefan Farfeleder, Andreas Krall, Edwin Steiner, Florian Brandner, Effective Compiler Generation by Architecture Description," ACM SIGPLAN Notices LCTES'06, Vol. 41, No. 7, pp145-152, June 2006.
  • G. Hadjiyiannis, S. Hanono, and S. Devadas, "ISDL: An Instruction set description language for retargetability," In Proc. of the ACM/IEEE Design Automation Conference(DAC), June 1997.
  • J. Gyllenhaal et al., "Optimization of Machine Descriptions for Efficient Use," In Proc. 29th Annual International Symposium on Microarchitecture, 1996.
  • C. Siska, "A Processor Description language supporting retargetable multi-pipeline DSP program development tools," In Proceedings of the International Symposium on System Synthesis(ISSS), Dec. 1998.

    • Low Power/Energy Management

  • PE#001: A. Rudenko, P. Reiher, G. J. Popek, and G. H. Kuenning, "The Remote Processing Framework for Portable Computer Power Saving," In ACM Symposium on Applied Computing, pp365∼372, Feb. 1999.
  • PE#002: M. Lee, V. Tiwari, S. Malik, M. Fujita, "Power Analysis and Minimization Techniques for Embedded DSP Software," IEEE Trans. on VLSI Systems, Vol. 5 No. 2, 1997.
  • Uli Kremer, "Compilers for Power and Energy Management," Tutorial ACM SIGPLAN PLDI2003, June 2003.
  • Uli Kremer, "Low Power/Power Compiler Optimizations," in Low-Power Electronics Design(Editor: Christian Piguet), CRC Press, 2005.
  • C. H. Hsu, Uli Kremer, "The Design, Implementation, and Evaluation of a Compiler Algorithm for CPU Energy Reduction," ACM SIGPLAN PLDI2003, June 2003.
  • Rainer Leupers, "Compiler Design Issues for Embedded Processors," IEEE Design & Test of Computers, July 2002.
  • Bernhard Egger, Chihun Kim, Choonki Jang, Yoonsung Nam, Jaejin Lee, and Sanglyul Min, A Dynamic Code Placement Technique for Scratch-pad Memory using Post-pass Optimization, In Proceedings of the Int. Conf. on Compilers, Architecture, and Synthesis for Embedded, Systems(CASES'06), Oct. 2006.
  • Jihong Kim, T. Simunic Rosing, "Power-aware resource management techniques for low-power embedded systems," in Handbook of Real-Time and Embedded Systems(Editors: I. Lee, J. Leung and S. Son), CRC Press, 2007.
  • T. Burd, R. Brodersen, "Energy Efficient CMOS Microprocessor Design," In the 28th Hawaii Int. Conf. on System Sciences(HICSS-95), Jan. 1995.
  • C. H. Hsu, U. Kremer, "Dynamic Voltage and Frequency Scaling for Scientific Applications," Int. Workshop on Languages and Compilers for Parallel Computing, August 2001.
  • Robert Muth, Saumya Debray, Scott Watterson, "Alto: A Link-Time Optimizer for the Compaq Alpha," Software Practice and Experience, Vol. 31, Jan. 2001.
  • Rajeshwari Banaker, et al, "Scratch-pad Memory: A Design Alternative for Cache on-Chip Memory in Embedded Systems," Proceedings of the 10th Int. Symposium on Hardware/Software Codesign, 2002.
  • Uli Kremer, J. Hicks, J. Rehg, "A Compilation Framework for Power and Energy Management on Mobile Computers," 14th LCPC2001, August 2001.

    • Virtual Machine Solutions

  • VM#001: Phillip Stanley-Marbell, Liviu Ifotode, "Scylla: A Smart Virtual Machine for Mobile Embedded Systems," In Proceedings of the 3rd IEEE Workshop on Moblie Computing Systems and Applications, pp41-50, 2000.
  • T. Lindholm and F.Yellin, The Java Virtual Machine Specification 2nd Edition, Addison-Wesley, 1999.
  • Bowen Alpern etc. al, "Jalapeno---a Compiler-Supported Java Virtual Machine for Servers," In ACM SIGPLAN 1999 Workshop on Compiler Support for System Software, May 1999.
  • T. Lindholm and F. Yellin, "The Java Virtual Machine Specification 2nd Edition," Addison-Wesley, 1999.
  • James E. Smith, Ravi Nair, "Virtual Machine: Versatile Platforms for Systems and Process," Morgan Kaufmann Publishers, 2005.
  • N. Shaylor, D. Simon, W. Bush, "A Java Virtual Architecture for Very Small Devices," ACM LCTES'03, pp34∼41, June 2003.
  • P. Devis, D. Culler, "Mate: A Tiny Virtual Machine for Sensor Networks", In Proceedings of the 10th International Conference Architectural Support for Programming Languages and Operating Systems, pp.111∼123, 2002.
  • R. Muller, G. Alonso, D. Kossmann, "A Virtual Machine for Sensor Networks," ACM EuroSys'07, pp145-158, March 2007.
  • Phillip Stanley-Marbell, Liviu Ifotode, "Scylla: A Smart Virtual Machine for Mobile Embedded Systems," In Proceedings of the 3rd IEEE Workshop on Mobile Computing Systems and Applications, pp41-50, 2000.
  • John Whaley, "Joeq: A Virtual Machine and Compiler Infrastructure," ACM JVME'03, pp58-66, June 2003.
  • Bill Venners, Inside the Java Virtual Machine, McGraw-Hill, 1998.
  • E. M. Gagnon and L. J. Hendren, "Sable VM: A research framework for the efficient execution of Java bytecode," In Proceedings of the Java Virtual Machine Research and Technology Symposium(JVM '01), pp27-40,April 2001.
  • Byung-Sun Yang and Soo-Mook Moon et. al, "LaTTe: A Java VM Just-in-Time Compiler with Fast and Efficient Register Allocation," Proceedings of the 1999 International Conference on Parallel Architecture and Compilation Techniques (PACT99), New Port Beach, CA, 1999
  • Y. Shi, D. Gregg,A. Beaty, and M. A. Ertl, "Vitrual Machine Showdown: Stack versus Registers," In VEE 2005, pp153-163, 2005.

    • Others

  • S. Furber, ARM System-on-Chip Architecture, Addison-Wesley, 2000.
  • G. Kane, J. Heirich, MIPS RISC Architecture, Prentice-Hall, 1992.
  • Richard D. Paul, "SPARC Architecture, Assembly Language Programming, and C," Prentice-Hall International Editions, 1994.
  • Associated Compiler Experts: http://www.ace.nl
  • Tool Interface Standard Committee, Executable and Linking Format(ELF) Specifications v1.2, 1995.
    • Last updated by KO. at 2:00pm on March-27, 2008.